1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and more particularly, the present invention relates to a synchronous semiconductor memory device including a duty cycle correction (DCC) circuit for correcting the duty cycle of a clock.
A claim of priority is made to Korean Patent Application No. 2003-3295, filed on 17 Jan. 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
In a synchronous semiconductor memory device that receives/outputs data in phase with an internal clock, the duty cycle of the internal clock is a factor that affects operational characteristics of the device. The duty cycle of a clock is defined as the ratio of the pulse width to the pulse duration of the clock.
In general, most digital clock applications, such as those used in the field of semiconductor integrated circuits, rely on clock duty cycles of 50%. A clock with a duty cycle of 50% is a clock in which high-level and low-level durations of each pulse of the clock are the same.
It is often necessary to precisely control the duty cycle of a clock. For example, in the case of a synchronous semiconductor memory device that outputs data in phase with a clock, the output data may be distorted if the clock duty cycle is not precisely adjusted to 50%. Accordingly, a duty cycle correction (DCC) circuit is used when necessary to adjust an input clock having duty cycle that is above or below 50% to obtain a clock signal having a duty cycle of 50%.
In the meantime, double data rate (DDR) synchronous semiconductor memory devices have been developed in an effort to increase operating speeds. The DDR allows data to be input or output at both rising and falling edges of a clock. Accordingly, precise adjustment of the clock duty cycle is especially important in the case of DDR synchronous semiconductor memory devices.
FIG. 1 illustrates a conventional scheme of correcting the duty cycle of an input clock signal CLK_IN. As shown in FIG. 1, the input clock signal CLK_IN is input to a DCC circuit 12 via an amplifier 11. The DCC circuit 12 corrects the duty cycle of the input clock signal CLK_IN and outputs an output signal CLK_OUT as the result of the correction.
Here, the amplifier 11 amplifies the voltage levels of the input CLK_IN to obtain an amplitude swing between a ground voltage VSS and a power supply voltage VDD.
FIG. 2 is a circuit diagram of the DCC circuit 12 of FIG. 1. Referring to FIG. 2, the DCC circuit 12 includes first through third inverters 210, 220, and 230. The first inverter 210 includes a PMOS transistor MP21 and an NMOS transistor MN22, and the second inverter 220 includes a PMOS transistor MP23 and an NMOS transistor MN24.
The first inverter 210 receives and inverts an input first clock signal CLK_A, and outputs the inverted result to a node N. The second inverter 220 receives and inverts an input second clock signal CLK_B, which is opposite in phase to the first clock signal CLK_A, and outputs the inverted result to the same node N. That is, the output terminal of the first inverter 210 and the output terminal of the second inverter 220 are both connected to the node N. The third inverter 230 inverts a signal received from the node N and outputs the inverted result as an output signal CLK_OUT. The output signal CLK_OUT is a clock signal having a corrected duty cycle.
However, process variations in the fabrication of semiconductor memory device may cause distortion in the duty cycle of the output clock signal. As previously mentioned, the signal CLK_IN output from the amplifier 11 is input directly to the DCC circuit 12 and the DCC circuit 12 corrects the duty cycle of the clock and outputs an output signal CLK_OUT as the result of the correction. Process variations can alter the slope of the signal CLK_IN output from the amplifier 11, and as a result, the signal CLK_IN output from the DCC circuit 12 can be distorted.
If the distortion of the duty cycle of a clock is beyond design margins that the system can handle, a fatal error may occur during the operation of the system.